`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SJTU
// Engineer: Yricky
// 
// Create Date: 2019/10/27 14:07:39
// Design Name: 
// Module Name: OctaSelect
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module OctaSelect(
    input [31:0] data_in,
    input select_clk,
    output [3:0] data_out,
    output [7:0] digit_sel
    );
    reg [3:0] data_out;
    reg [7:0] digit_sel;
    reg [2:0]q;
    
    always @(posedge select_clk)
    q<=q+1;
    
    always @(*)
    case(q)
    
    3'b000:
    begin
    data_out<=data_in[3:0];
    digit_sel<=8'b00000001;
    end
    
    3'b001:
    begin
    data_out<=data_in[7:4];
     digit_sel<=8'b00000010;
    end
    
    3'b010:
    begin
    data_out<=data_in[11:8];
     digit_sel<=8'b00000100;
    end
    
    3'b011:
    begin
    data_out<=data_in[15:12];
    digit_sel<=8'b00001000;
    end
    
    3'b100:
    begin
    data_out<=data_in[19:16];
    digit_sel<=8'b00010000;
    end
    
    3'b101:
    begin
    data_out<=data_in[23:20];
     digit_sel<=8'b00100000;
    end
    
    3'b110:
    begin
    data_out<=data_in[27:24];
     digit_sel<=8'b01000000;
    end
    
    3'b111:
    begin
    data_out<=data_in[31:28];
    digit_sel<=8'b10000000;
    end
    
    
    
    default:
    data_out<=4'b0000;
    endcase 
endmodule
